How did the Zip Chip and RocketChip accelerators work for the Apple II?How do accelerators and CPU cards work on the Apple II?Apple IIgs: Hardware implementation of RAM shadowingWhy does my Macintosh SE FDHD only see 2 of the 4 megabytes of RAM?What are the major differences between the ColecoVision and the SG-1000?Is the Apple II “No-Slot Clock” compatible with the Thunderclock?Largest practical motherboard for early computersWhat happened to ZIP RAM?How did 2-chip CPUs work?What are the Ultra-Highres registers in ECS and AGA for?Late 1970s and 6502 chip facilities for operating systems

Is it possible to commute 34km daily?

instead of pressurizing an entire spacesuit with oxygen could oxygen just pressurize the head and the rest of the body be pressurized with water?

Why do Climate activists attack public transport?

Why is double encryption that's equivalent to single encryption no better than single encryption?

How are astronauts in the ISS protected from electric shock?

Rational Number RNG

How can I more clearly ask people to accomodate for my autism?

Why am I having wrong IPs in my DNS?

How to play a devious character when you are not personally devious?

A jazzy one-liner

My cat gets angry and scared at me if I stand

What is the basis for the custom to stand or sit by Vayivarech Dovid?

Is the ''yoi'' meaning ''ready'' when doing karate the same as the ''yoi'' which means nice/good?

How can an immortal member of the nobility be prevented from taking the throne?

Ubuntu 19.10 - release hour?

What can I use for input conversion instead of scanf?

Does recycling lead to less jobs?

How to inflict ESD-damage on a board?

Does animal blood, esp. human, really have similar salinity as ocean water, and does that prove anything about evolution?

Company asks (more than once) if I can involve family members in project

Do European politicians typically put their pronouns on their social media pages?

Asimov's story where a man's speech contains no information

Is it safe to plug one travel adapter into another?

What examples are there of unrelated physical quantities measured in the same units?



How did the Zip Chip and RocketChip accelerators work for the Apple II?


How do accelerators and CPU cards work on the Apple II?Apple IIgs: Hardware implementation of RAM shadowingWhy does my Macintosh SE FDHD only see 2 of the 4 megabytes of RAM?What are the major differences between the ColecoVision and the SG-1000?Is the Apple II “No-Slot Clock” compatible with the Thunderclock?Largest practical motherboard for early computersWhat happened to ZIP RAM?How did 2-chip CPUs work?What are the Ultra-Highres registers in ECS and AGA for?Late 1970s and 6502 chip facilities for operating systems






.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty
margin-bottom:0;









9

















Though there is already a similar question on the site, this one is more specific to these chips and their technical implementation.



There were two accelerators for the Apple II series that were drop-in replacements for the 6502: The Zip Chip and the RocketChip. Both were apparently similar in architecture as the RC was produced by people who left Zip, but sold a product that ran 25% faster (5MHz/10MHz versus 4MHz/8MHz).



I'm curious how these chips actually worked. Similarities that I'm aware of are that:



  1. They both maintain their own internal clock; the mainboard is not modified in this regard.

  2. They utilize some caching technology; I don't believe they mirror main RAM like some accelerators (e.g. Titan and TransWarp, from what I understand).

  3. They are aware of memory addresses that require slowdowns to stock 1MHz speeds (e.g. slot 6 for 5.25" floppy access, though these were configurable).

What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down? What about speed of RAM on the motherboard? Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?



Any details would be appreciated. I always felt that I had a good understanding of how it worked, but lately I've been curious if there were actual technical implementation notes to be found anywhere.










share|improve this question
































    9

















    Though there is already a similar question on the site, this one is more specific to these chips and their technical implementation.



    There were two accelerators for the Apple II series that were drop-in replacements for the 6502: The Zip Chip and the RocketChip. Both were apparently similar in architecture as the RC was produced by people who left Zip, but sold a product that ran 25% faster (5MHz/10MHz versus 4MHz/8MHz).



    I'm curious how these chips actually worked. Similarities that I'm aware of are that:



    1. They both maintain their own internal clock; the mainboard is not modified in this regard.

    2. They utilize some caching technology; I don't believe they mirror main RAM like some accelerators (e.g. Titan and TransWarp, from what I understand).

    3. They are aware of memory addresses that require slowdowns to stock 1MHz speeds (e.g. slot 6 for 5.25" floppy access, though these were configurable).

    What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down? What about speed of RAM on the motherboard? Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?



    Any details would be appreciated. I always felt that I had a good understanding of how it worked, but lately I've been curious if there were actual technical implementation notes to be found anywhere.










    share|improve this question




























      9












      9








      9


      1






      Though there is already a similar question on the site, this one is more specific to these chips and their technical implementation.



      There were two accelerators for the Apple II series that were drop-in replacements for the 6502: The Zip Chip and the RocketChip. Both were apparently similar in architecture as the RC was produced by people who left Zip, but sold a product that ran 25% faster (5MHz/10MHz versus 4MHz/8MHz).



      I'm curious how these chips actually worked. Similarities that I'm aware of are that:



      1. They both maintain their own internal clock; the mainboard is not modified in this regard.

      2. They utilize some caching technology; I don't believe they mirror main RAM like some accelerators (e.g. Titan and TransWarp, from what I understand).

      3. They are aware of memory addresses that require slowdowns to stock 1MHz speeds (e.g. slot 6 for 5.25" floppy access, though these were configurable).

      What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down? What about speed of RAM on the motherboard? Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?



      Any details would be appreciated. I always felt that I had a good understanding of how it worked, but lately I've been curious if there were actual technical implementation notes to be found anywhere.










      share|improve this question















      Though there is already a similar question on the site, this one is more specific to these chips and their technical implementation.



      There were two accelerators for the Apple II series that were drop-in replacements for the 6502: The Zip Chip and the RocketChip. Both were apparently similar in architecture as the RC was produced by people who left Zip, but sold a product that ran 25% faster (5MHz/10MHz versus 4MHz/8MHz).



      I'm curious how these chips actually worked. Similarities that I'm aware of are that:



      1. They both maintain their own internal clock; the mainboard is not modified in this regard.

      2. They utilize some caching technology; I don't believe they mirror main RAM like some accelerators (e.g. Titan and TransWarp, from what I understand).

      3. They are aware of memory addresses that require slowdowns to stock 1MHz speeds (e.g. slot 6 for 5.25" floppy access, though these were configurable).

      What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down? What about speed of RAM on the motherboard? Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?



      Any details would be appreciated. I always felt that I had a good understanding of how it worked, but lately I've been curious if there were actual technical implementation notes to be found anywhere.







      hardware apple-ii cpu






      share|improve this question














      share|improve this question











      share|improve this question




      share|improve this question










      asked May 29 at 17:16









      bjbbjb

      6,41919 silver badges77 bronze badges




      6,41919 silver badges77 bronze badges























          1 Answer
          1






          active

          oldest

          votes


















          11



















          I'm curious how these chips actually worked. Similarities [...]




          They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold wires connecting all of the internal parts"




          What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down?




          That wouldn't bring much, as most 6502 cycles are memory cycles, so no speed up without any cache.



          In case of Zip/Rocket-Chip it has been an 8 KiB tagged cache realized with two 6264 (alike) RAM chips. One as 8 KiB Cache, the other providing a tag byte for each location.



          Easy to see when looking at the last page of the IIc+ schematics. Apple licenced the Zip-Chip for the IIc+, but changed the design to use standard, of the shelf, RAMs, putting all logic into a gate array.




          What about speed of RAM on the motherboard?




          Stayed as before. Every access was synced and slowed down to motherboard speed. The speedup was only as long as data was read and the data to be read was within the cache.



          The hardware was basically (*1) an 8 KiB RAM storing bytewise data plus an equally sized tag RAM. 8 KiB means 13 bit address. So the tag RAM stored the upper 3 bit of any address plus a flag if the data is valid or not.



          The handling logic was rather straight forward cache implementation.



          • Address presented during a cycle (*2) checked against exclusions.

            • If it was an excluded address (slowed down) the CPU was synced with main RAM and the access was performed

            • If not, direction was checked

              • If it was a write the CPU was synchronized and data was written into main RAM and cache at the same time, as well as A13..A15 into tag RAM.

              • If it was a read, the tag RAM was checked at the corresponding address (A0..A12)

              • If the tag fitted (A13..A15 equal and valid) the entry was handed to the CPU, cycle finished at set speed (4 MHz).

              • On non-fit, the CPU was synchronized and slowed, data was read from RAM simultaneous to CPU and cache, tag is updated.



          Done.



          As a result worst case is a CPU fully synchronized with main memory, effectively running at 1 MHz. Whenever a byte gets used twice a speedup may happen - i.e. as soon as more than one consecutive memory access (like executing a two byte instruction) happens. Any code will run during first pass at 1 MHz and later at up to 4 MHz



          Speedup resulted mostly from the fact that vast majority of all memory cycles a 6502 issues are for reading code and code is usually repeated. Data is even in best case (only ZP access) below 1/3rd - in real situations it'll considerable less than 20%. More of 2/3rd thereof usually read cycles, resulting in less than 10% of all cycles being writes.



          So as long as the majority of executed code (and often used data) fits into 8 Kib (*3), speedup will be quite close to the speed selected (4 MHz). For most software it will work much like shadowing on an Apple IIgs. A bit slower on first execution but speed up wenn the cache is loaded - and slowed for any writes.




          Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?




          Video did run from the motherboard memory (during the second half, as before).




          *1 - This will be very basic, not going into each detail.



          *2 - Each and every cycle on a 6502 is a memory cycle.



          *3 - doesn't have much aliasing issues.






          share|improve this answer




























          • Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

            – Tom Hawtin - tackline
            Jun 10 at 17:41











          • @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

            – Raffzahn
            Jun 10 at 19:43












          Your Answer








          StackExchange.ready(function()
          var channelOptions =
          tags: "".split(" "),
          id: "648"
          ;
          initTagRenderer("".split(" "), "".split(" "), channelOptions);

          StackExchange.using("externalEditor", function()
          // Have to fire editor after snippets, if snippets enabled
          if (StackExchange.settings.snippets.snippetsEnabled)
          StackExchange.using("snippets", function()
          createEditor();
          );

          else
          createEditor();

          );

          function createEditor()
          StackExchange.prepareEditor(
          heartbeatType: 'answer',
          autoActivateHeartbeat: false,
          convertImagesToLinks: false,
          noModals: true,
          showLowRepImageUploadWarning: true,
          reputationToPostImages: null,
          bindNavPrevention: true,
          postfix: "",
          imageUploader:
          brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
          contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/4.0/"u003ecc by-sa 4.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
          allowUrls: true
          ,
          noCode: true, onDemand: true,
          discardSelector: ".discard-answer"
          ,immediatelyShowMarkdownHelp:true
          );



          );














          draft saved

          draft discarded
















          StackExchange.ready(
          function ()
          StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fretrocomputing.stackexchange.com%2fquestions%2f11149%2fhow-did-the-zip-chip-and-rocketchip-accelerators-work-for-the-apple-ii%23new-answer', 'question_page');

          );

          Post as a guest















          Required, but never shown


























          1 Answer
          1






          active

          oldest

          votes








          1 Answer
          1






          active

          oldest

          votes









          active

          oldest

          votes






          active

          oldest

          votes









          11



















          I'm curious how these chips actually worked. Similarities [...]




          They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold wires connecting all of the internal parts"




          What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down?




          That wouldn't bring much, as most 6502 cycles are memory cycles, so no speed up without any cache.



          In case of Zip/Rocket-Chip it has been an 8 KiB tagged cache realized with two 6264 (alike) RAM chips. One as 8 KiB Cache, the other providing a tag byte for each location.



          Easy to see when looking at the last page of the IIc+ schematics. Apple licenced the Zip-Chip for the IIc+, but changed the design to use standard, of the shelf, RAMs, putting all logic into a gate array.




          What about speed of RAM on the motherboard?




          Stayed as before. Every access was synced and slowed down to motherboard speed. The speedup was only as long as data was read and the data to be read was within the cache.



          The hardware was basically (*1) an 8 KiB RAM storing bytewise data plus an equally sized tag RAM. 8 KiB means 13 bit address. So the tag RAM stored the upper 3 bit of any address plus a flag if the data is valid or not.



          The handling logic was rather straight forward cache implementation.



          • Address presented during a cycle (*2) checked against exclusions.

            • If it was an excluded address (slowed down) the CPU was synced with main RAM and the access was performed

            • If not, direction was checked

              • If it was a write the CPU was synchronized and data was written into main RAM and cache at the same time, as well as A13..A15 into tag RAM.

              • If it was a read, the tag RAM was checked at the corresponding address (A0..A12)

              • If the tag fitted (A13..A15 equal and valid) the entry was handed to the CPU, cycle finished at set speed (4 MHz).

              • On non-fit, the CPU was synchronized and slowed, data was read from RAM simultaneous to CPU and cache, tag is updated.



          Done.



          As a result worst case is a CPU fully synchronized with main memory, effectively running at 1 MHz. Whenever a byte gets used twice a speedup may happen - i.e. as soon as more than one consecutive memory access (like executing a two byte instruction) happens. Any code will run during first pass at 1 MHz and later at up to 4 MHz



          Speedup resulted mostly from the fact that vast majority of all memory cycles a 6502 issues are for reading code and code is usually repeated. Data is even in best case (only ZP access) below 1/3rd - in real situations it'll considerable less than 20%. More of 2/3rd thereof usually read cycles, resulting in less than 10% of all cycles being writes.



          So as long as the majority of executed code (and often used data) fits into 8 Kib (*3), speedup will be quite close to the speed selected (4 MHz). For most software it will work much like shadowing on an Apple IIgs. A bit slower on first execution but speed up wenn the cache is loaded - and slowed for any writes.




          Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?




          Video did run from the motherboard memory (during the second half, as before).




          *1 - This will be very basic, not going into each detail.



          *2 - Each and every cycle on a 6502 is a memory cycle.



          *3 - doesn't have much aliasing issues.






          share|improve this answer




























          • Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

            – Tom Hawtin - tackline
            Jun 10 at 17:41











          • @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

            – Raffzahn
            Jun 10 at 19:43















          11



















          I'm curious how these chips actually worked. Similarities [...]




          They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold wires connecting all of the internal parts"




          What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down?




          That wouldn't bring much, as most 6502 cycles are memory cycles, so no speed up without any cache.



          In case of Zip/Rocket-Chip it has been an 8 KiB tagged cache realized with two 6264 (alike) RAM chips. One as 8 KiB Cache, the other providing a tag byte for each location.



          Easy to see when looking at the last page of the IIc+ schematics. Apple licenced the Zip-Chip for the IIc+, but changed the design to use standard, of the shelf, RAMs, putting all logic into a gate array.




          What about speed of RAM on the motherboard?




          Stayed as before. Every access was synced and slowed down to motherboard speed. The speedup was only as long as data was read and the data to be read was within the cache.



          The hardware was basically (*1) an 8 KiB RAM storing bytewise data plus an equally sized tag RAM. 8 KiB means 13 bit address. So the tag RAM stored the upper 3 bit of any address plus a flag if the data is valid or not.



          The handling logic was rather straight forward cache implementation.



          • Address presented during a cycle (*2) checked against exclusions.

            • If it was an excluded address (slowed down) the CPU was synced with main RAM and the access was performed

            • If not, direction was checked

              • If it was a write the CPU was synchronized and data was written into main RAM and cache at the same time, as well as A13..A15 into tag RAM.

              • If it was a read, the tag RAM was checked at the corresponding address (A0..A12)

              • If the tag fitted (A13..A15 equal and valid) the entry was handed to the CPU, cycle finished at set speed (4 MHz).

              • On non-fit, the CPU was synchronized and slowed, data was read from RAM simultaneous to CPU and cache, tag is updated.



          Done.



          As a result worst case is a CPU fully synchronized with main memory, effectively running at 1 MHz. Whenever a byte gets used twice a speedup may happen - i.e. as soon as more than one consecutive memory access (like executing a two byte instruction) happens. Any code will run during first pass at 1 MHz and later at up to 4 MHz



          Speedup resulted mostly from the fact that vast majority of all memory cycles a 6502 issues are for reading code and code is usually repeated. Data is even in best case (only ZP access) below 1/3rd - in real situations it'll considerable less than 20%. More of 2/3rd thereof usually read cycles, resulting in less than 10% of all cycles being writes.



          So as long as the majority of executed code (and often used data) fits into 8 Kib (*3), speedup will be quite close to the speed selected (4 MHz). For most software it will work much like shadowing on an Apple IIgs. A bit slower on first execution but speed up wenn the cache is loaded - and slowed for any writes.




          Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?




          Video did run from the motherboard memory (during the second half, as before).




          *1 - This will be very basic, not going into each detail.



          *2 - Each and every cycle on a 6502 is a memory cycle.



          *3 - doesn't have much aliasing issues.






          share|improve this answer




























          • Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

            – Tom Hawtin - tackline
            Jun 10 at 17:41











          • @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

            – Raffzahn
            Jun 10 at 19:43













          11














          11










          11










          I'm curious how these chips actually worked. Similarities [...]




          They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold wires connecting all of the internal parts"




          What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down?




          That wouldn't bring much, as most 6502 cycles are memory cycles, so no speed up without any cache.



          In case of Zip/Rocket-Chip it has been an 8 KiB tagged cache realized with two 6264 (alike) RAM chips. One as 8 KiB Cache, the other providing a tag byte for each location.



          Easy to see when looking at the last page of the IIc+ schematics. Apple licenced the Zip-Chip for the IIc+, but changed the design to use standard, of the shelf, RAMs, putting all logic into a gate array.




          What about speed of RAM on the motherboard?




          Stayed as before. Every access was synced and slowed down to motherboard speed. The speedup was only as long as data was read and the data to be read was within the cache.



          The hardware was basically (*1) an 8 KiB RAM storing bytewise data plus an equally sized tag RAM. 8 KiB means 13 bit address. So the tag RAM stored the upper 3 bit of any address plus a flag if the data is valid or not.



          The handling logic was rather straight forward cache implementation.



          • Address presented during a cycle (*2) checked against exclusions.

            • If it was an excluded address (slowed down) the CPU was synced with main RAM and the access was performed

            • If not, direction was checked

              • If it was a write the CPU was synchronized and data was written into main RAM and cache at the same time, as well as A13..A15 into tag RAM.

              • If it was a read, the tag RAM was checked at the corresponding address (A0..A12)

              • If the tag fitted (A13..A15 equal and valid) the entry was handed to the CPU, cycle finished at set speed (4 MHz).

              • On non-fit, the CPU was synchronized and slowed, data was read from RAM simultaneous to CPU and cache, tag is updated.



          Done.



          As a result worst case is a CPU fully synchronized with main memory, effectively running at 1 MHz. Whenever a byte gets used twice a speedup may happen - i.e. as soon as more than one consecutive memory access (like executing a two byte instruction) happens. Any code will run during first pass at 1 MHz and later at up to 4 MHz



          Speedup resulted mostly from the fact that vast majority of all memory cycles a 6502 issues are for reading code and code is usually repeated. Data is even in best case (only ZP access) below 1/3rd - in real situations it'll considerable less than 20%. More of 2/3rd thereof usually read cycles, resulting in less than 10% of all cycles being writes.



          So as long as the majority of executed code (and often used data) fits into 8 Kib (*3), speedup will be quite close to the speed selected (4 MHz). For most software it will work much like shadowing on an Apple IIgs. A bit slower on first execution but speed up wenn the cache is loaded - and slowed for any writes.




          Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?




          Video did run from the motherboard memory (during the second half, as before).




          *1 - This will be very basic, not going into each detail.



          *2 - Each and every cycle on a 6502 is a memory cycle.



          *3 - doesn't have much aliasing issues.






          share|improve this answer

















          I'm curious how these chips actually worked. Similarities [...]




          They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold wires connecting all of the internal parts"




          What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down?




          That wouldn't bring much, as most 6502 cycles are memory cycles, so no speed up without any cache.



          In case of Zip/Rocket-Chip it has been an 8 KiB tagged cache realized with two 6264 (alike) RAM chips. One as 8 KiB Cache, the other providing a tag byte for each location.



          Easy to see when looking at the last page of the IIc+ schematics. Apple licenced the Zip-Chip for the IIc+, but changed the design to use standard, of the shelf, RAMs, putting all logic into a gate array.




          What about speed of RAM on the motherboard?




          Stayed as before. Every access was synced and slowed down to motherboard speed. The speedup was only as long as data was read and the data to be read was within the cache.



          The hardware was basically (*1) an 8 KiB RAM storing bytewise data plus an equally sized tag RAM. 8 KiB means 13 bit address. So the tag RAM stored the upper 3 bit of any address plus a flag if the data is valid or not.



          The handling logic was rather straight forward cache implementation.



          • Address presented during a cycle (*2) checked against exclusions.

            • If it was an excluded address (slowed down) the CPU was synced with main RAM and the access was performed

            • If not, direction was checked

              • If it was a write the CPU was synchronized and data was written into main RAM and cache at the same time, as well as A13..A15 into tag RAM.

              • If it was a read, the tag RAM was checked at the corresponding address (A0..A12)

              • If the tag fitted (A13..A15 equal and valid) the entry was handed to the CPU, cycle finished at set speed (4 MHz).

              • On non-fit, the CPU was synchronized and slowed, data was read from RAM simultaneous to CPU and cache, tag is updated.



          Done.



          As a result worst case is a CPU fully synchronized with main memory, effectively running at 1 MHz. Whenever a byte gets used twice a speedup may happen - i.e. as soon as more than one consecutive memory access (like executing a two byte instruction) happens. Any code will run during first pass at 1 MHz and later at up to 4 MHz



          Speedup resulted mostly from the fact that vast majority of all memory cycles a 6502 issues are for reading code and code is usually repeated. Data is even in best case (only ZP access) below 1/3rd - in real situations it'll considerable less than 20%. More of 2/3rd thereof usually read cycles, resulting in less than 10% of all cycles being writes.



          So as long as the majority of executed code (and often used data) fits into 8 Kib (*3), speedup will be quite close to the speed selected (4 MHz). For most software it will work much like shadowing on an Apple IIgs. A bit slower on first execution but speed up wenn the cache is loaded - and slowed for any writes.




          Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?




          Video did run from the motherboard memory (during the second half, as before).




          *1 - This will be very basic, not going into each detail.



          *2 - Each and every cycle on a 6502 is a memory cycle.



          *3 - doesn't have much aliasing issues.







          share|improve this answer















          share|improve this answer




          share|improve this answer








          edited May 30 at 7:25

























          answered May 29 at 18:27









          RaffzahnRaffzahn

          72.6k8 gold badges181 silver badges303 bronze badges




          72.6k8 gold badges181 silver badges303 bronze badges















          • Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

            – Tom Hawtin - tackline
            Jun 10 at 17:41











          • @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

            – Raffzahn
            Jun 10 at 19:43

















          • Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

            – Tom Hawtin - tackline
            Jun 10 at 17:41











          • @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

            – Raffzahn
            Jun 10 at 19:43
















          Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

          – Tom Hawtin - tackline
          Jun 10 at 17:41





          Pedantry: Every 6502 cycle is a memory cycle (it may, however, not be useful).

          – Tom Hawtin - tackline
          Jun 10 at 17:41













          @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

          – Raffzahn
          Jun 10 at 19:43





          @TomHawtin-tackline Since this is not about instruction execution but memory cycles, the add on would be itself quite useless, wouldn't it? Lets keep focused.

          – Raffzahn
          Jun 10 at 19:43


















          draft saved

          draft discarded















































          Thanks for contributing an answer to Retrocomputing Stack Exchange!


          • Please be sure to answer the question. Provide details and share your research!

          But avoid


          • Asking for help, clarification, or responding to other answers.

          • Making statements based on opinion; back them up with references or personal experience.

          To learn more, see our tips on writing great answers.




          draft saved


          draft discarded














          StackExchange.ready(
          function ()
          StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fretrocomputing.stackexchange.com%2fquestions%2f11149%2fhow-did-the-zip-chip-and-rocketchip-accelerators-work-for-the-apple-ii%23new-answer', 'question_page');

          );

          Post as a guest















          Required, but never shown





















































          Required, but never shown














          Required, but never shown












          Required, but never shown







          Required, but never shown

































          Required, but never shown














          Required, but never shown












          Required, but never shown







          Required, but never shown









          Popular posts from this blog

          Tamil (spriik) Luke uk diar | Nawigatjuun

          Align equal signs while including text over equalitiesAMS align: left aligned text/math plus multicolumn alignmentMultiple alignmentsAligning equations in multiple placesNumbering and aligning an equation with multiple columnsHow to align one equation with another multline equationUsing \ in environments inside the begintabularxNumber equations and preserving alignment of equal signsHow can I align equations to the left and to the right?Double equation alignment problem within align enviromentAligned within align: Why are they right-aligned?

          Training a classifier when some of the features are unknownWhy does Gradient Boosting regression predict negative values when there are no negative y-values in my training set?How to improve an existing (trained) classifier?What is effect when I set up some self defined predisctor variables?Why Matlab neural network classification returns decimal values on prediction dataset?Fitting and transforming text data in training, testing, and validation setsHow to quantify the performance of the classifier (multi-class SVM) using the test data?How do I control for some patients providing multiple samples in my training data?Training and Test setTraining a convolutional neural network for image denoising in MatlabShouldn't an autoencoder with #(neurons in hidden layer) = #(neurons in input layer) be “perfect”?