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VHDL: What is correct way to model open collector output for FPGA?

Multiplexing an I2C bus between two masters on a Xilinx FPGASetting up an ATtiny45 as I2C master - SDA stuck lowHow to wire output buses togetherI2C communication with AVR - how to let the lines “float”?I2C SCL ground issueHow SPI and I2C latch data?I2C ACK bit glitchWhy do I2C lines use open drain driver instead of tri-state drivers?1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSimHow to verify a VHDL I2C master?

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margin-bottom:0;

7

1

$begingroup$

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?


2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

fpga vhdl i2c testbench

share|improve this question

asked Jun 13 at 20:31

quantum231quantum231

4,1111515 gold badges6666 silver badges132132 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  intel.com/content/www/us/en/programmable/support/…
  $endgroup$
  – Eugene Sh.
  Jun 13 at 20:34
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  The main difficulty is simulation side of this
  $endgroup$
  – quantum231
  Jun 14 at 5:00
  

  
  
  
  

add a comment
 | 

7

1

$begingroup$

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?


2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

fpga vhdl i2c testbench

share|improve this question

asked Jun 13 at 20:31

quantum231quantum231

4,1111515 gold badges6666 silver badges132132 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  intel.com/content/www/us/en/programmable/support/…
  $endgroup$
  – Eugene Sh.
  Jun 13 at 20:34
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  The main difficulty is simulation side of this
  $endgroup$
  – quantum231
  Jun 14 at 5:00
  

  
  
  
  

add a comment
 | 

$begingroup$

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?


2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

fpga vhdl i2c testbench

share|improve this question

asked Jun 13 at 20:31

quantum231quantum231

4,1111515 gold badges6666 silver badges132132 bronze badges

$endgroup$

share|improve this question

asked Jun 13 at 20:31

quantum231quantum231

4,1111515 gold badges6666 silver badges132132 bronze badges

share|improve this question

asked Jun 13 at 20:31

quantum231quantum231

4,1111515 gold badges6666 silver badges132132 bronze badges

asked Jun 13 at 20:31

quantum231quantum231

4,1111515 gold badges6666 silver badges132132 bronze badges

asked Jun 13 at 20:31

quantum231quantum231

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3 Answers
3

active

oldest

votes

12

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  But is 'Z' + 'H' = '1'? This is the confusing part. In other words, if both receiver and transmitter are driving 'Z' onto SDA and then one of them reads the value on SDA, it should get '1' since it is pulled high externally right?
  $endgroup$
  – quantum231
  Jun 14 at 4:54
  

  
  
  
  


• 
  
  
  

  
  5
  

  
  
  
  
  
  

  
  $begingroup$
  Z + H = H. But to_01(H) = 1, so H is seen as 1 by just about any subsequent gate or process.
  $endgroup$
  – Brian Drummond
  Jun 14 at 9:55
  

  
  
  
  

add a comment
 | 

6

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

$endgroup$

• 
  
  
  

  
  2
  

  
  
  
  
  
  

  
  $begingroup$
  Why 5 lines of Verilog when you can just do assign DOUT = ENABLE ? 1'b0 : 1'bz;? (Also, your ENABLE is acting as a DISABLE, making the code a bit confusing).
  $endgroup$
  – The Photon
  Jun 13 at 22:12
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ThePhoton The code comes from Xilinx's website (as mentioned in my answer).
  $endgroup$
  – KingDuken
  Jun 14 at 0:33
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Thanks King. Here the question is solely from simulation perspective. If both transmitter and receiver are driving 'Z' onto the SDA and one of them reads in the SDA, if it is not pulled high then it shall read in 'Z'. If it is pulled high out should read '1'. The problem is, if we pull high externally using '1'then it shall clash with SDA being driven to '0' as happens with open collectors. Can we use 'H'? Don't know since never used it. If driven externally to 'H' and internally to 'Z', will reading internally give '1' or 'H'?
  $endgroup$
  – quantum231
  Jun 14 at 4:55
  
  

  
  
  
  

add a comment
 | 

5

$begingroup$

Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write

LIBRARY altera;
USE altera.altera_primitives_components.all; 
sda: opndrn PORT MAP (
a_in => sda_wire,
a_out => sda_pin
);

This shouldn't make any difference on a bidir IO pin, but it may make a difference if you need to use an output-only pin or migrate your design to ASIC. It makes your code vendor-specific though.

share|improve this answer

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges

$endgroup$

add a comment
 | 

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12

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  But is 'Z' + 'H' = '1'? This is the confusing part. In other words, if both receiver and transmitter are driving 'Z' onto SDA and then one of them reads the value on SDA, it should get '1' since it is pulled high externally right?
  $endgroup$
  – quantum231
  Jun 14 at 4:54
  

  
  
  
  


• 
  
  
  

  
  5
  

  
  
  
  
  
  

  
  $begingroup$
  Z + H = H. But to_01(H) = 1, so H is seen as 1 by just about any subsequent gate or process.
  $endgroup$
  – Brian Drummond
  Jun 14 at 9:55
  

  
  
  
  

add a comment
 | 

12

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  But is 'Z' + 'H' = '1'? This is the confusing part. In other words, if both receiver and transmitter are driving 'Z' onto SDA and then one of them reads the value on SDA, it should get '1' since it is pulled high externally right?
  $endgroup$
  – quantum231
  Jun 14 at 4:54
  

  
  
  
  


• 
  
  
  

  
  5
  

  
  
  
  
  
  

  
  $begingroup$
  Z + H = H. But to_01(H) = 1, so H is seen as 1 by just about any subsequent gate or process.
  $endgroup$
  – Brian Drummond
  Jun 14 at 9:55
  

  
  
  
  

add a comment
 | 

$begingroup$

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs.
You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

share|improve this answer

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

$endgroup$

sda <= 'Z' when dout='1' else '0';

sda <='H';

share|improve this answer

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

answered Jun 13 at 20:40

TEMLIBTEMLIB

2,22211 gold badge88 silver badges1717 bronze badges

6

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

$endgroup$

• 
  
  
  

  
  2
  

  
  
  
  
  
  

  
  $begingroup$
  Why 5 lines of Verilog when you can just do assign DOUT = ENABLE ? 1'b0 : 1'bz;? (Also, your ENABLE is acting as a DISABLE, making the code a bit confusing).
  $endgroup$
  – The Photon
  Jun 13 at 22:12
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ThePhoton The code comes from Xilinx's website (as mentioned in my answer).
  $endgroup$
  – KingDuken
  Jun 14 at 0:33
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Thanks King. Here the question is solely from simulation perspective. If both transmitter and receiver are driving 'Z' onto the SDA and one of them reads in the SDA, if it is not pulled high then it shall read in 'Z'. If it is pulled high out should read '1'. The problem is, if we pull high externally using '1'then it shall clash with SDA being driven to '0' as happens with open collectors. Can we use 'H'? Don't know since never used it. If driven externally to 'H' and internally to 'Z', will reading internally give '1' or 'H'?
  $endgroup$
  – quantum231
  Jun 14 at 4:55
  
  

  
  
  
  

add a comment
 | 

6

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

$endgroup$

• 
  
  
  

  
  2
  

  
  
  
  
  
  

  
  $begingroup$
  Why 5 lines of Verilog when you can just do assign DOUT = ENABLE ? 1'b0 : 1'bz;? (Also, your ENABLE is acting as a DISABLE, making the code a bit confusing).
  $endgroup$
  – The Photon
  Jun 13 at 22:12
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @ThePhoton The code comes from Xilinx's website (as mentioned in my answer).
  $endgroup$
  – KingDuken
  Jun 14 at 0:33
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  Thanks King. Here the question is solely from simulation perspective. If both transmitter and receiver are driving 'Z' onto the SDA and one of them reads in the SDA, if it is not pulled high then it shall read in 'Z'. If it is pulled high out should read '1'. The problem is, if we pull high externally using '1'then it shall clash with SDA being driven to '0' as happens with open collectors. Can we use 'H'? Don't know since never used it. If driven externally to 'H' and internally to 'Z', will reading internally give '1' or 'H'?
  $endgroup$
  – quantum231
  Jun 14 at 4:55
  
  

  
  
  
  

add a comment
 | 

$begingroup$

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

share|improve this answer

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

$endgroup$

dout <= 'Z' when din='1' else '0';

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

share|improve this answer

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

answered Jun 13 at 20:43

KingDukenKingDuken

1,66922 gold badges66 silver badges1717 bronze badges

5

$begingroup$

Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write

LIBRARY altera;
USE altera.altera_primitives_components.all; 
sda: opndrn PORT MAP (
a_in => sda_wire,
a_out => sda_pin
);

This shouldn't make any difference on a bidir IO pin, but it may make a difference if you need to use an output-only pin or migrate your design to ASIC. It makes your code vendor-specific though.

share|improve this answer

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges

$endgroup$

add a comment
 | 

5

$begingroup$

Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write

LIBRARY altera;
USE altera.altera_primitives_components.all; 
sda: opndrn PORT MAP (
a_in => sda_wire,
a_out => sda_pin
);

This shouldn't make any difference on a bidir IO pin, but it may make a difference if you need to use an output-only pin or migrate your design to ASIC. It makes your code vendor-specific though.

share|improve this answer

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges

$endgroup$

add a comment
 | 

$begingroup$

Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write

LIBRARY altera;
USE altera.altera_primitives_components.all; 
sda: opndrn PORT MAP (
a_in => sda_wire,
a_out => sda_pin
);

This shouldn't make any difference on a bidir IO pin, but it may make a difference if you need to use an output-only pin or migrate your design to ASIC. It makes your code vendor-specific though.

share|improve this answer

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges

$endgroup$

LIBRARY altera;
USE altera.altera_primitives_components.all; 
sda: opndrn PORT MAP (
a_in => sda_wire,
a_out => sda_pin
);

share|improve this answer

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges

answered Jun 14 at 8:04

Dmitry GrigoryevDmitry Grigoryev

19.9k22 gold badges3131 silver badges8080 bronze badges