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What is meaning of active low input in combinational logic circuits?
Gate Output as a Switch?Cross-coupled logic gates and timingWill the schematic I created for my project work?How does a non-FPGA (ie a PC with a CPU, RAM, hard drive) mimic logic gates?What are the rules for combining transistors to form digital circuits?Why do I experience a voltage drop between logic gates when combining multiple gates (7408 and 7402)Using 3-state buffers for multiplexingHow can output from a single logic gate/DIP switch supply input for multiple gates?
.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty
margin-bottom:0;
$begingroup$
I am currently doing self study on combinational logic circuits. I encountered few terms like active low output, active low input. I understood what active low output means (putting not gates at output side). I guess active low means putting not gate at input side.
It will be very helpful if some one can explain this using an example (note that I have knowledge of encoders, decoders, Multiplexers so you can use these in your example).
digital-logic integrated-circuit input
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
$endgroup$
add a comment
|
$begingroup$
I am currently doing self study on combinational logic circuits. I encountered few terms like active low output, active low input. I understood what active low output means (putting not gates at output side). I guess active low means putting not gate at input side.
It will be very helpful if some one can explain this using an example (note that I have knowledge of encoders, decoders, Multiplexers so you can use these in your example).
digital-logic integrated-circuit input
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
$endgroup$
1
$begingroup$
"Active" means ENABLED. Active_high needs a high, +3.3v, a ONE, a TRUE. Active_low needs a low, 0.0v, a ZERO, a FALSE.
$endgroup$
– analogsystemsrf
Sep 18 at 17:01
1
$begingroup$
And, there's arguments about terminology. Because some people (me) would say that "active low" means that a low voltage is interpreted as true or one.
$endgroup$
– TimWescott
Sep 18 at 17:16
1
$begingroup$
indeed. You can define True as any level you wish.
$endgroup$
– analogsystemsrf
Sep 18 at 17:32
add a comment
|
$begingroup$
I am currently doing self study on combinational logic circuits. I encountered few terms like active low output, active low input. I understood what active low output means (putting not gates at output side). I guess active low means putting not gate at input side.
It will be very helpful if some one can explain this using an example (note that I have knowledge of encoders, decoders, Multiplexers so you can use these in your example).
digital-logic integrated-circuit input
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
$endgroup$
I am currently doing self study on combinational logic circuits. I encountered few terms like active low output, active low input. I understood what active low output means (putting not gates at output side). I guess active low means putting not gate at input side.
It will be very helpful if some one can explain this using an example (note that I have knowledge of encoders, decoders, Multiplexers so you can use these in your example).
digital-logic integrated-circuit input
digital-logic integrated-circuit input
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
edited Sep 19 at 1:06
Voltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
43.8k12 gold badges45 silver badges125 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
asked Sep 18 at 16:33
ShawnShawn
333 bronze badges
333 bronze badges
1
$begingroup$
"Active" means ENABLED. Active_high needs a high, +3.3v, a ONE, a TRUE. Active_low needs a low, 0.0v, a ZERO, a FALSE.
$endgroup$
– analogsystemsrf
Sep 18 at 17:01
1
$begingroup$
And, there's arguments about terminology. Because some people (me) would say that "active low" means that a low voltage is interpreted as true or one.
$endgroup$
– TimWescott
Sep 18 at 17:16
1
$begingroup$
indeed. You can define True as any level you wish.
$endgroup$
– analogsystemsrf
Sep 18 at 17:32
add a comment
|
1
$begingroup$
"Active" means ENABLED. Active_high needs a high, +3.3v, a ONE, a TRUE. Active_low needs a low, 0.0v, a ZERO, a FALSE.
$endgroup$
– analogsystemsrf
Sep 18 at 17:01
1
$begingroup$
And, there's arguments about terminology. Because some people (me) would say that "active low" means that a low voltage is interpreted as true or one.
$endgroup$
– TimWescott
Sep 18 at 17:16
1
$begingroup$
indeed. You can define True as any level you wish.
$endgroup$
– analogsystemsrf
Sep 18 at 17:32
1
1
$begingroup$
"Active" means ENABLED. Active_high needs a high, +3.3v, a ONE, a TRUE. Active_low needs a low, 0.0v, a ZERO, a FALSE.
$endgroup$
– analogsystemsrf
Sep 18 at 17:01
$begingroup$
"Active" means ENABLED. Active_high needs a high, +3.3v, a ONE, a TRUE. Active_low needs a low, 0.0v, a ZERO, a FALSE.
$endgroup$
– analogsystemsrf
Sep 18 at 17:01
1
1
$begingroup$
And, there's arguments about terminology. Because some people (me) would say that "active low" means that a low voltage is interpreted as true or one.
$endgroup$
– TimWescott
Sep 18 at 17:16
$begingroup$
And, there's arguments about terminology. Because some people (me) would say that "active low" means that a low voltage is interpreted as true or one.
$endgroup$
– TimWescott
Sep 18 at 17:16
1
1
$begingroup$
indeed. You can define True as any level you wish.
$endgroup$
– analogsystemsrf
Sep 18 at 17:32
$begingroup$
indeed. You can define True as any level you wish.
$endgroup$
– analogsystemsrf
Sep 18 at 17:32
add a comment
|
3 Answers
3
active
oldest
votes
$begingroup$
It means the signal is inverted (like a NOT gate). Let's take this 555 timer below as an example
Picture can be found here... Not my picture (and excuse the massive compression for this picture, hence the ugly pixels)
Say that a signal that goes to this pin is a 1 or HIGH. Since Pin 4 is active low, it will end up being a 0 or LOW for this pin. The opposite is true: If the signal leading up to the pin is 0 or LOW, then Pin 4 will be 1 or HIGH.
The purpose for a signal to be active low is to have some type of external logic device to turn off the signal. CPLDs are a good example of external logic that would shut off a device by sending a signal to an active low pin. You might thinking, "Why don't we just simply make it active high instead?" That's a valid question and I'm not really sure to be honest but if I had to guess, it could be to just simply save power.
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
$endgroup$
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
1
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
add a comment
|
$begingroup$
There are two things:
- The signal level
- What the signal means, ie assertion
The signal level is either digital Low or High
The signal meaning is attached to either Low or High, so we say the signal is asserted low or the signal is asserted high. Usually a bar or a slash indicates a low signal assertion level.
In the case above the reset is asserted low, so "reseting" happens when the signal is brought low. Since we could also reset while the signal is brought high, it is important to track the assertion.
It is especially important in HDL's to track the signal assertion level. Which is why you should label all of your signals. I've typically seen adding a _L or _H suffix to signal names to indicate the assertion level. In the case above it would be RESET_L. Even adding assertion suffixes in schematics can be helpful
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
$endgroup$
add a comment
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$begingroup$
Active LOW means that a 0 V level is considered to be a logic 1.
For instance, consider a logic input tied high using a pullup resistor and pulled to ground through a pushbutton switch.
Whenever the switch is not pressed, the input is at the pullup voltage, 5 V for example.
When the switch is pressed, the input is pulled to ground.
That input can be considered active low, because the low level means that the button has been pressed (logic 1)
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
$endgroup$
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3 Answers
3
active
oldest
votes
3 Answers
3
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
It means the signal is inverted (like a NOT gate). Let's take this 555 timer below as an example
Picture can be found here... Not my picture (and excuse the massive compression for this picture, hence the ugly pixels)
Say that a signal that goes to this pin is a 1 or HIGH. Since Pin 4 is active low, it will end up being a 0 or LOW for this pin. The opposite is true: If the signal leading up to the pin is 0 or LOW, then Pin 4 will be 1 or HIGH.
The purpose for a signal to be active low is to have some type of external logic device to turn off the signal. CPLDs are a good example of external logic that would shut off a device by sending a signal to an active low pin. You might thinking, "Why don't we just simply make it active high instead?" That's a valid question and I'm not really sure to be honest but if I had to guess, it could be to just simply save power.
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
$endgroup$
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
1
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
add a comment
|
$begingroup$
It means the signal is inverted (like a NOT gate). Let's take this 555 timer below as an example
Picture can be found here... Not my picture (and excuse the massive compression for this picture, hence the ugly pixels)
Say that a signal that goes to this pin is a 1 or HIGH. Since Pin 4 is active low, it will end up being a 0 or LOW for this pin. The opposite is true: If the signal leading up to the pin is 0 or LOW, then Pin 4 will be 1 or HIGH.
The purpose for a signal to be active low is to have some type of external logic device to turn off the signal. CPLDs are a good example of external logic that would shut off a device by sending a signal to an active low pin. You might thinking, "Why don't we just simply make it active high instead?" That's a valid question and I'm not really sure to be honest but if I had to guess, it could be to just simply save power.
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
$endgroup$
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
1
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
add a comment
|
$begingroup$
It means the signal is inverted (like a NOT gate). Let's take this 555 timer below as an example
Picture can be found here... Not my picture (and excuse the massive compression for this picture, hence the ugly pixels)
Say that a signal that goes to this pin is a 1 or HIGH. Since Pin 4 is active low, it will end up being a 0 or LOW for this pin. The opposite is true: If the signal leading up to the pin is 0 or LOW, then Pin 4 will be 1 or HIGH.
The purpose for a signal to be active low is to have some type of external logic device to turn off the signal. CPLDs are a good example of external logic that would shut off a device by sending a signal to an active low pin. You might thinking, "Why don't we just simply make it active high instead?" That's a valid question and I'm not really sure to be honest but if I had to guess, it could be to just simply save power.
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
$endgroup$
It means the signal is inverted (like a NOT gate). Let's take this 555 timer below as an example
Picture can be found here... Not my picture (and excuse the massive compression for this picture, hence the ugly pixels)
Say that a signal that goes to this pin is a 1 or HIGH. Since Pin 4 is active low, it will end up being a 0 or LOW for this pin. The opposite is true: If the signal leading up to the pin is 0 or LOW, then Pin 4 will be 1 or HIGH.
The purpose for a signal to be active low is to have some type of external logic device to turn off the signal. CPLDs are a good example of external logic that would shut off a device by sending a signal to an active low pin. You might thinking, "Why don't we just simply make it active high instead?" That's a valid question and I'm not really sure to be honest but if I had to guess, it could be to just simply save power.
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
edited Sep 18 at 16:55
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
answered Sep 18 at 16:50
KingDukenKingDuken
1,6892 gold badges6 silver badges17 bronze badges
1,6892 gold badges6 silver badges17 bronze badges
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
1
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
add a comment
|
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
1
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
$begingroup$
Suppose i have i decoder , say 3 input decoder .If i connect not gates at each input respectively then it is active low input otherwise it is active high input by default ?
$endgroup$
– Shawn
Sep 18 at 16:52
1
1
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
$begingroup$
The active low inversion is typically built into the CMOS of the same chip. There's no external NOT gates that cause a signal to be active low. But yes, if you had that scenario, it would behave the same way (with exception of extremely small time differences).
$endgroup$
– KingDuken
Sep 18 at 16:54
add a comment
|
$begingroup$
There are two things:
- The signal level
- What the signal means, ie assertion
The signal level is either digital Low or High
The signal meaning is attached to either Low or High, so we say the signal is asserted low or the signal is asserted high. Usually a bar or a slash indicates a low signal assertion level.
In the case above the reset is asserted low, so "reseting" happens when the signal is brought low. Since we could also reset while the signal is brought high, it is important to track the assertion.
It is especially important in HDL's to track the signal assertion level. Which is why you should label all of your signals. I've typically seen adding a _L or _H suffix to signal names to indicate the assertion level. In the case above it would be RESET_L. Even adding assertion suffixes in schematics can be helpful
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
$endgroup$
add a comment
|
$begingroup$
There are two things:
- The signal level
- What the signal means, ie assertion
The signal level is either digital Low or High
The signal meaning is attached to either Low or High, so we say the signal is asserted low or the signal is asserted high. Usually a bar or a slash indicates a low signal assertion level.
In the case above the reset is asserted low, so "reseting" happens when the signal is brought low. Since we could also reset while the signal is brought high, it is important to track the assertion.
It is especially important in HDL's to track the signal assertion level. Which is why you should label all of your signals. I've typically seen adding a _L or _H suffix to signal names to indicate the assertion level. In the case above it would be RESET_L. Even adding assertion suffixes in schematics can be helpful
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
$endgroup$
add a comment
|
$begingroup$
There are two things:
- The signal level
- What the signal means, ie assertion
The signal level is either digital Low or High
The signal meaning is attached to either Low or High, so we say the signal is asserted low or the signal is asserted high. Usually a bar or a slash indicates a low signal assertion level.
In the case above the reset is asserted low, so "reseting" happens when the signal is brought low. Since we could also reset while the signal is brought high, it is important to track the assertion.
It is especially important in HDL's to track the signal assertion level. Which is why you should label all of your signals. I've typically seen adding a _L or _H suffix to signal names to indicate the assertion level. In the case above it would be RESET_L. Even adding assertion suffixes in schematics can be helpful
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
$endgroup$
There are two things:
- The signal level
- What the signal means, ie assertion
The signal level is either digital Low or High
The signal meaning is attached to either Low or High, so we say the signal is asserted low or the signal is asserted high. Usually a bar or a slash indicates a low signal assertion level.
In the case above the reset is asserted low, so "reseting" happens when the signal is brought low. Since we could also reset while the signal is brought high, it is important to track the assertion.
It is especially important in HDL's to track the signal assertion level. Which is why you should label all of your signals. I've typically seen adding a _L or _H suffix to signal names to indicate the assertion level. In the case above it would be RESET_L. Even adding assertion suffixes in schematics can be helpful
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
edited Sep 18 at 17:32
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
answered Sep 18 at 17:03
Voltage SpikeVoltage Spike
43.8k12 gold badges45 silver badges125 bronze badges
43.8k12 gold badges45 silver badges125 bronze badges
add a comment
|
add a comment
|
$begingroup$
Active LOW means that a 0 V level is considered to be a logic 1.
For instance, consider a logic input tied high using a pullup resistor and pulled to ground through a pushbutton switch.
Whenever the switch is not pressed, the input is at the pullup voltage, 5 V for example.
When the switch is pressed, the input is pulled to ground.
That input can be considered active low, because the low level means that the button has been pressed (logic 1)
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
$endgroup$
add a comment
|
$begingroup$
Active LOW means that a 0 V level is considered to be a logic 1.
For instance, consider a logic input tied high using a pullup resistor and pulled to ground through a pushbutton switch.
Whenever the switch is not pressed, the input is at the pullup voltage, 5 V for example.
When the switch is pressed, the input is pulled to ground.
That input can be considered active low, because the low level means that the button has been pressed (logic 1)
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
$endgroup$
add a comment
|
$begingroup$
Active LOW means that a 0 V level is considered to be a logic 1.
For instance, consider a logic input tied high using a pullup resistor and pulled to ground through a pushbutton switch.
Whenever the switch is not pressed, the input is at the pullup voltage, 5 V for example.
When the switch is pressed, the input is pulled to ground.
That input can be considered active low, because the low level means that the button has been pressed (logic 1)
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
$endgroup$
Active LOW means that a 0 V level is considered to be a logic 1.
For instance, consider a logic input tied high using a pullup resistor and pulled to ground through a pushbutton switch.
Whenever the switch is not pressed, the input is at the pullup voltage, 5 V for example.
When the switch is pressed, the input is pulled to ground.
That input can be considered active low, because the low level means that the button has been pressed (logic 1)
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
answered Sep 18 at 16:44
jsotolajsotola
1,5841 gold badge8 silver badges11 bronze badges
1,5841 gold badge8 silver badges11 bronze badges
add a comment
|
add a comment
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1
$begingroup$
"Active" means ENABLED. Active_high needs a high, +3.3v, a ONE, a TRUE. Active_low needs a low, 0.0v, a ZERO, a FALSE.
$endgroup$
– analogsystemsrf
Sep 18 at 17:01
1
$begingroup$
And, there's arguments about terminology. Because some people (me) would say that "active low" means that a low voltage is interpreted as true or one.
$endgroup$
– TimWescott
Sep 18 at 17:16
1
$begingroup$
indeed. You can define True as any level you wish.
$endgroup$
– analogsystemsrf
Sep 18 at 17:32