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Though there is already a similar question on the site, this one is more specific to these chips and their technical implementation.

There were two accelerators for the Apple II series that were drop-in replacements for the 6502: The Zip Chip and the RocketChip. Both were apparently similar in architecture as the RC was produced by people who left Zip, but sold a product that ran 25% faster (5MHz/10MHz versus 4MHz/8MHz).

I'm curious how these chips actually worked. Similarities that I'm aware of are that:

1. They both maintain their own internal clock; the mainboard is not modified in this regard.


2. They utilize some caching technology; I don't believe they mirror main RAM like some accelerators (e.g. Titan and TransWarp, from what I understand).


3. They are aware of memory addresses that require slowdowns to stock 1MHz speeds (e.g. slot 6 for 5.25" floppy access, though these were configurable).

What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down? What about speed of RAM on the motherboard? Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?

Any details would be appreciated. I always felt that I had a good understanding of how it worked, but lately I've been curious if there were actual technical implementation notes to be found anywhere.

I'm curious how these chips actually worked. Similarities [...]

They are so similar, that Zip Technologies even won the case against Rocket-Chips manufacturer Bits & Pieces. Just, the manual doesn't tell a lot about the inner workings. Only that it's a "technological marvel" with the equivalent of "350 integrated logic chips" and "hundrets of tiny gold wires connecting all of the internal parts"

What I'm curious about is if it was simply a faster clock cadence with a MMU to know where to slow down?

That wouldn't bring much, as most 6502 cycles are memory cycles, so no speed up without any cache.

In case of Zip/Rocket-Chip it has been an 8 KiB tagged cache realized with two 6264 (alike) RAM chips. One as 8 KiB Cache, the other providing a tag byte for each location.

Easy to see when looking at the last page of the IIc+ schematics. Apple licenced the Zip-Chip for the IIc+, but changed the design to use standard, of the shelf, RAMs, putting all logic into a gate array.

What about speed of RAM on the motherboard?

Stayed as before. Every access was synced and slowed down to motherboard speed. The speedup was only as long as data was read and the data to be read was within the cache.

The hardware was basically (*1) an 8 KiB RAM storing bytewise data plus an equally sized tag RAM. 8 KiB means 13 bit address. So the tag RAM stored the upper 3 bit of any address plus a flag if the data is valid or not.

The handling logic was rather straight forward cache implementation.

• Address presented during a cycle (*2) checked against exclusions.
  
  
  • If it was an excluded address (slowed down) the CPU was synced with main RAM and the access was performed
  
  
  • If not, direction was checked
    
    
    • If it was a write the CPU was synchronized and data was written into main RAM and cache at the same time, as well as A13..A15 into tag RAM.
    
    
    • If it was a read, the tag RAM was checked at the corresponding address (A0..A12)
    
    
    • If the tag fitted (A13..A15 equal and valid) the entry was handed to the CPU, cycle finished at set speed (4 MHz).
    
    
    • On non-fit, the CPU was synchronized and slowed, data was read from RAM simultaneous to CPU and cache, tag is updated.
    
    
  
  

Done.

As a result worst case is a CPU fully synchronized with main memory, effectively running at 1 MHz. Whenever a byte gets used twice a speedup may happen - i.e. as soon as more than one consecutive memory access (like executing a two byte instruction) happens. Any code will run during first pass at 1 MHz and later at up to 4 MHz

Speedup resulted mostly from the fact that vast majority of all memory cycles a 6502 issues are for reading code and code is usually repeated. Data is even in best case (only ZP access) below 1/3rd - in real situations it'll considerable less than 20%. More of 2/3rd thereof usually read cycles, resulting in less than 10% of all cycles being writes.

So as long as the majority of executed code (and often used data) fits into 8 Kib (*3), speedup will be quite close to the speed selected (4 MHz). For most software it will work much like shadowing on an Apple IIgs. A bit slower on first execution but speed up wenn the cache is loaded - and slowed for any writes.

Was the video "interrupt" simply pulling the /RDY line as per a motherboard clock and thus the speed of the actual CPU didn't matter?

Video did run from the motherboard memory (during the second half, as before).

*1 - This will be very basic, not going into each detail.

*2 - Each and every cycle on a 6502 is a memory cycle.

*3 - doesn't have much aliasing issues.